Caltech
Ares J. Rosakis Ares J. Rosakis
Theodore von Kármán Professor of Aeronautics and Mechanical Engineering

Research Interests

CGS Interferometry as a Full-Field, Real-Time, and In-Situ Wafer Inspection and Reliability Tool
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Collaborator: S. Suresh, MIT; Y. Huang, U Ill; E. Ustundag, Ohio State U; Staff: T-S. Park; Student: M. Brow, Caltech

As the semiconductor industry retools for the processing of larger diameter (300 mm) wafers with smaller circuit features (0.13 µm or less), the need for accurate full-field, in-situ and real-time inspection and reliability analysis tools becomes imperative.

In this work, we concentrate on the development of a vibration insensitive interferometric method designed especially to meet these new inspection and stress management challenges. Coherent Gradient Sensing (CGS) interferometry is used to study wafer planarity issues that arise throughout the entire wafer processing cycle. In particular, CGS is used to measure the non-uniform curvature tensor evolution of entire wafer surfaces in real-time during the cycle, as an in-situ process diagnostic. Issues addressed in this work include a) the use of CGS during film deposition as a means of continuously monitoring film uniformity and coverage within a deposition reactor, b) its use in conjunction with elaborate stress analysis tools for the measurement of stresses on thin films and lines during wafer processing or thermal cycling and, c) its ability of mapping highly non-uniform, non-linear deformations and curvature bifurcations that become important as wafer sizes scale up. X-ray microdiffraction measurements, performed at Lawrence Berkeley, are used for validating the curvature and stress fields independently obtained from CGS interferometry.

Throughout the project, emphasis is given to the suitability of the method as an in-situ process diagnostic. Other applications of the technique, include deformation measurements in the die and packaging levels and the study of large deformation and gravity effects and wafer support design in large, thin wafers.

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